A display panel generally has a large number of pixels arranged in a two dimensional array. To drive the display panel, an active matrix substrate includes a large number of switching elements made of thin-film transistors or TFTs to activate the pixels.
It is known in the art that each switching element has a drain electrode, a source electrode and a gate electrode and each pixel has a pixel electrode and a storage capacitor to store electric charges between the pixel electrode and a common line. As the size of the TFT-driven display panel becomes large and its resolution becomes high, the addressing time of the pixels becomes very short and the capacitance loading of the display panel becomes high, causing the charging time of the display pixel to decrease significantly.
Each pixel in the array of pixels may be configured as disclosed, for example, in Lai, U.S. Pat. No. 7,250,992 and in its continuation U.S. Pat. No. 7,345,717, both of which are assigned to AU Optronics Corp., the parent company of the assignee of the current application, and both of which are hereby incorporated by reference in their entireties. As shown in Lai FIG. 1, each pixel may comprise a rectangular region defined by a pair of gate lines (scan lines) and a pair of data lines (signal lines). Disposed within the rectangular region may be a TFT serving as a switching device and a pixel electrode. The gate of the TFT may extend from one of the gate lines that define the pixel, the source of the TFT may extend from one of the data lines that define the pixel, and the drain of the TFT may be electrically connected to the pixel electrode through a via.
As further described in Lai, the gate and data lines, the TFTs, and the pixel electrodes may be formed using a multi-layer process. For example, the gate lines and TFT gates may be formed in a first metal process layer, and the data lines and TFT sources and drains may be formed in a second metal process layer. As described in Lai, the presence of overlapping metal layers will result in parasitic capacitance between the source and gate and between the drain and gate of the TFT. Shifts in the alignment of the two process layers may cause the values of these parasitic capacitances to change, producing undesirable effects during the operation of the display. As disclosed in Lai, a compensation capacitor may be formed by a compensation structure that extends from at least one of the gate and the gate line and that overlaps a portion of the drain. The configuration of the compensation structure may be such that the sum of the gate-drain parasitic capacitance and the capacitance between the drain and the compensation structure maintains a substantially constant value as the alignment between the two metal process layers shifts.
The TFTs, gate and data lines, and pixel electrodes may be formed in a multilayer structure such as that shown in FIGS. 1 and 2E of Lai et al., U.S. Pat. No. 7,170,092 and in its division U.S. Pat. No. 7,507,612, both of which are assigned to AU Optronics Corp., the parent company of the assignee of the current application, and both of which are hereby incorporated by reference in their entireties. The multilayer structure may comprise a first conducting layer, a first insulating layer, a semiconductor layer, a doped semiconductor layer, and a second conducting layer disposed in sequence on the substrate. It may further comprise a second insulating layer and a pixel electrode disposed on the second insulating layer. The first conducting layer may comprise at least one of a gate line or a gate electrode. The doped semiconductor layer may comprise a source and a drain. The second conducting layer may comprise a source electrode and a drain electrode. The multilayer structure may be formed using a series of wet and dry etching processes, for example as disclosed in Lai et al. FIGS. 2A-2D.
Additional techniques for forming TFTs are disclosed in Chen, U.S. Pat. No. 7,652,285, which is assigned to AU Optronics Corp., the parent company of the assignee of the current application, and hereby incorporated by reference in its entirety. As disclosed in Chen, to form the channel of the TFT, the second metal layer is etched in order to open a portion of the second metal layer over the gate electrode and to separate the source region and drain region. This etching can be performed in multiple ways, including the back-channel etching process disclosed for example in Chen FIGS. 2A-2E and the etch stop process disclosed for example in Chen FIGS. 5A-5D and 6.
Accordingly, it is desired to develop a display panel that realizes improved performance while maintaining a comparatively low manufacturing cost.